1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a technique of processing a gate electrode of the semiconductor device with etching to form an impurity region in a semiconductor layer.
2. Description of the Related Art
In a display device using liquid crystal, a part with a large-screen over 20 inches, which is typified by a liquid crystal display TV, has been put to practical use. In recent years, a liquid crystal display device integrated with a driving circuit has been realized with a TFT in which a polycrystalline silicon film is used as an active layer.
However, a defect is pointed out that a thin film transistor (TFT) using a polycrystalline silicon film has a low withstanding pressure in drain junction to increase junction leak current (hereinafter, OFF-leak current). It is known that it is effective to form a lightly doped region (LDD) structure as measures.
The phenomenon is pointed out as trouble that high electric field is generated in the vicinity of the drain region, then, a generated hot carrier is trapped by a gate insulating film on the LDD region, and then, device characteristics such as threshold voltage are greatly fluctuated and lowered. In order to prevent the deterioration due to hot carriers, a TFT in which a gate electrode is overlapped with an LDD (lightly doped drain) region is disclosed (for example, referred to as Japanese Patent Laid-Open No. 2000-294787). The TFT with the gate overlapped LDD structure has higher current driving ability compared to a TFT with a normal LDD structure, and effectively eases the high electric field in the vicinity of the drain region to suppress the deterioration due to hot carriers.
However, in the case of the TFT with the gate overlapped LDD structure disclosed in the above publication, after an impurity region for forming an LDD region is formed in a semiconductor layer, a gate electrode is overlapped with the LDD region. Accordingly, the portion overlapping with the gate electrode cannot be accurately formed along with the miniaturization of design rule.
On the other hand, as a method for manufacturing a TFT with a gate overlapping LDD structure in a self-aligning manner, the technique is disclosed that a conductive layer that has at least two layer laminated is subjected to exposure once and etching plural times to make the upper layer and the lower layer have different sizes, and then, ion doping is conducted with utilizing the differences in size and thickness to form an LDD region overlapped with a gate electrode in a self-aligning (for example, referred to as Japanese Patent Laid-Open No. 2002-14337).
It is preferable that a length of the LDD (a length with respect to the channel length) is optimized depending on driving voltage of the TFT in order to maximally show the function of the LDD overlapped with the gate electrode as measures against the deterioration in TFT characteristics due to hot carriers. Consequently, it is necessary to adjust the length of the LDD (a length with respect to the channel length) to an optimum length for easing effectively the high electric field in the vicinity of the drain region.
The length of the LDD overlapped with the gate electrode is controlled in accordance with a shape of a conductive layer that becomes a mask during ion doping for the LDD. A conductive layer of two-layer lamination is subjected to an etching process and only the upper layer of the conductive layer is selectively subjected to an anisotropic etching process to form the mask. Consequently, it is important that a selection ratio of a material that forms the conductive layer is high in the anisotropic etching process.
In short, it is necessary to consider the relation between etching gas and the material that is an object to be processed. If the selection ratio is low, a portion that needs no etching is etched to have problems that a desired shape cannot be obtained and each shape is not uniform. In addition, conditions in the process of the etching process cannot be controlled precisely. Consequently, reliability of a semiconductor device is lowered and yield is also decreased.